As seen in FIG. 1, a conventional flash memory device, such as that fabricated by Toshiba in Japan, or the ETOX flash memory device of Intel in the U.S.A., comprises a planar channel on which an insulation film 3, a floating gate (or storage electrode) 4, an inter-electrode insulation film 5, and a control electrode 6 are laminated in that order. With the recent great advances in various electronic appliances and mobile electronic equipment, the degree of integration of memory devices has been required to increase. Even though the memory size can be increased from a given technology node by applying an MLC (Multi Level Cell) technique, the size of the nonvolatile flash memory device must be reduced. However, the size reduction of the flash memory device may cause a lithographic problem, leading to the incapability to precisely control the size of a CD (Critical Dimension), and thus to CDE (CD Error).
In addition, as one cell element becomes close to another, cross-talk occurs therebetween, causing an operational error of the memory device and an increase in threshold voltage distribution. The narrower the distribution of threshold voltages according to the writing/erasing operation of cell elements, the better. However, the above-mentioned problems increase as the memory device decreases in size. Thus, the production yield also decreases. Particularly, as shown in FIG. 2, the floating electrode is made from polysilicon, consisting of a plurality of grains which differ in direction from one to another. In the case where a gate has a large area, that is, in the case in which the degree of integration is low, a number of grains which are variable in crystal direction exist in one cell storage electrode, so that the characteristics of the grains are equalized in each cell element. That is, none of the grains in a particular grain direction are predominant over any other, resulting in an improvement in the uniformity of characteristics over cell elements.
Despite the recent requirement for a high degree of integration, the thickness of the floating gate of the cell element has not tended to decrease because the coupling ratio between the control electrode and the floating electrode (or gate) must be maintained at approximately 0.6 or greater. Because the height of the floating gate has not decreased despite the size reduction of memory devices, cross-talk based on parasitic capacitance between cell elements has increased and the grain size has not decreased. As the cell elements decrease in size, the structure thereof is highly apt to undergo mechanical stresses from various thin films deposited thereon.
Suggested in the present invention is a structure which comprises simple elements and which can be fabricated through a process that is compatible with a conventional one, and which can solve the problems encountered in the prior arts, that is, can exhibit a narrow threshold voltage distribution, reduced cross-talk, and decreased mechanical stresses. If the floating gate decreases in thickness according to the miniaturization of cell elements, the coupling ratio is reduced. An attempt has been made to maintain the coupling ratio while reducing the thickness of the floating gate.
U.S. Pat. No. 6,765,258B1 (entitled “Stack-gate flash memory cell structure and contactless flash memory arrays therefor”) employs a spacer formation technology to realize a floating-gate structure with a thinner floating-gate layer formed in a center and a thicker floating-gate layer formed at the edge. This floating-gate structure requires additional spacer formation technology and is still likely to exhibit increased cross-talk with the adjacent cell due to the large thickness of the edge of the floating gate. This floating gate structure is different from that of the present invention, and does not exhibit excellence in terms of effect or process.
Even though the method is different than that of the present invention, a flash memory device having reduced cross-talk between neighboring cells is disclosed in U.S. Pat. No. 6,693,009B1 (entitled “Flash memory cell with minimized floating gate to drain/source overlap for minimizing charge leakage”). Out of a stack of a control electrode and a floating electrode, formed using a given technology node, only the floating electrode is laterally etched away to form an undercut, thereby suggesting a structure with a (reduced floating to drain/source overlap?). In this structure, charge leakage from the floating gate is minimized during programming/erasing of the flash memory cell. However, the device in this structure may operate erroneously because the undercut at the sidewall may eliminate the overlap between the source/drain and the floating gate. With regard to the object of minimizing only the floating gate to drain/source overlap, the length of the overlap can be precisely controlled by source/drain ion implantation into a dummy spacer rather than by etching a sidewall of the floating gate.
One of the advantages from the multilayer floating gate structure of the present invention is the improvement of the durability of the memory device by effectively absorbing mechanical stresses onto the grain boundary of polysilicon, the area of which is increased as a multilayer structure is formed. In this context, the advantages of such a multilayer structure can be found in the literature. An article issued in IEEE Trans. on Electron Devices, October 1998 (entitled “Effects of buffer layer structure on polysilicon buffer LOCOS for the isolation of submicron silicon devices”) sheds light on polysilicon buffered LOCOS, a conventional element isolation technology. In the article, problems, such as the formation of pin holes, caused by mechanical stresses can be solved by employing a multiple polysilicon layer, instead of a single polysilicon layer, as a buffer layer.
Flash memory devices are in great demand as household appliances and mobile electronic devices develop rapidly. Flash memory devices having gates 100 nm long have been developed and are now produced on an industrial scale. Mass production is expected for 60-nm process flash memory devices, which is beyond a 70-nm process, in the near future. Particularly, NAND type flash memory devices are expected to be developed using a 45 nm process. Major problems accompanying the reduction in gate length include the distribution of threshold voltage of the device which conducts programming/erasing processes, and cross-talk between the cell elements thereof. A decrease in gate length means a reduction in the size of the patterns formed through a lithographic technique. Problems with the photolithography and etching processes for reducing the size of patterns bring about errors into the critical dimension, causing a large distribution of device characteristics within and between wafers and between lots.
Particularly, threshold voltages after programming/erasing must be uniform, but show a large distribution in practice, resulting in a decrease in production yield. The distribution of threshold voltage is a variable which must be controlled because it has great importance for a flash memory device process. The distribution of threshold voltage, as mentioned above, generally increases with the reduction of device size. One of the factors determining the increase is the grain size of a polysilicon storage electrode. While the area of a storage electrode decreases with the reduction of device size, polysilicon grains are not reduced in size in the storage electrode. Accordingly, grains of a polysilicon storage electrode tend to decrease in number as the cell elements are decreased in size. Generally, only one to several grains exist in one cell on a 70-nm technology node. A polysilicon storage electrode consists of a plurality of grains, crystal directions of which are randomly formed. If different in crystal direction, grains differ from one to another in interface charge thereof at boundaries with tunneling insulation films immediately below. In the case of a storage electrode having a large area, there are a number of grains that have various crystal directions. Thus, each cell element has a storage electrode in which a variety of interface charges from various grains are averaged, so that interface charge characteristics are uniform over the cells.
However, grains within the storage electrode decrease in number as the cell decreases in size, increasing the possibility that grains in a particular direction will be predominant over grains in other directions. This results in a decrease in the uniformity of threshold voltage between cells. In other words, the distribution of threshold voltage increases. In this way, conventional flash cell devices have an increased distribution of threshold voltage as they decrease in size.
Further, the polysilicon floating gate of the conventional flash device structure does not decrease in thickness although the gate area of the device is decreased because the coupling ratio between the control electrode and the floating storage electrode must be maintained at about 0.6 or higher. As mentioned above, a large thickness of the floating gate causes an increase in cross-talk between cells, giving rise to an increase in false cell operation and threshold voltage distribution and thus a decrease in production yield.